AO-40 RUDAK Photos

The purpose of this meeting was to perform an initial test-fit of the Rudak module to the spaceframe, and to verify as many of the interfaces between Rudak and the rest of the satellite as possible. With outstanding support from the staff at the integration facility, it was a very productive weekend!

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  Bdale Garbee, KB0G, happy that the Rudak flight module is communicating with a simulated groundstation at the 10Mhz IF frequencies during testing just prior to integration of the module with the spacecraft. Bdale and Robert Diersing, N5AHD, had worked until almost the last possible minute debugging and testing the Rudak Boot Loader firmware, which is used to load the operating system and housekeeping software.
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  The Rudak flight module, meeting P3D for the first time. Lyle Johnson, WA7GXD, is holding the module, while Lou McFadin, W5DID, and Chuck Green, N0ADI, discuss clearance and mounting issues.
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  Lou putting in screws, while Lyle holds the module, and Jennifer assists.
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  Jennifer drives the official torque screw driver. Jennifer is the builder and maintainer of the spacecraft's wiring harness, and was present to assist us with mechanical and electrical interface issues all weekend.
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  The view of P3D from the table where most of the Rudak tests were conducted. The team at the lab provided a row of tables just outside the cleanroom for us to use to hold all our laptop computers, documentation, and other test paraphenalia. Jim White, WD0E, is in the foreground, Jennifer is working on the RF cabling to Rudak one bay around to the right.
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  Harold Price, NK6K, exhuberant at the news that his operating system kernal has successfully loaded on both Rudak flight CPU's. The two cables coming out of the Rudak module and heading for the ceiling are the ground support interface cables that ran between the two CPU's and the two notebook computers outside the clean room that were used to initiate and control the various software tests.
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  Debugging the GPS power control interface. Harold's portable oscilloscope is showing reality, rather than what anyone wants to see. This was one of about three relatively minor problems that were discovered and dealt with during this trip... which is exactly why we were there! Harold thinks Lyle is a dead ringer for Alexander Graham Bell in this shot... :-) Barry Baines, WD4ASW, looks over Harold's shoulder. Barry and Steve Bible, N7HPR, showed up for a few days, assisted our efforts over the weekend.

The purpose of this meeting was to test the Rudak bootroms (RBL), get the operating system (SCOS) running on the engineering unit CPU board, and test as much of the fully integrated flight and flight backup hardware as possible. It was a very productive weekend!

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  Jim White, WD0E, looks on as Robert Diersing, N5AHD, runs tests on his RBL (Rudak Boot Loader) firmware. RBL resides in fused-link PROM on the CPU boards, and provides the minimal command functions and upload features needed by the Rudak command team to control the system after a reset and bootstrap the operating system. In the lower right, the flight hardware stack is visible on the corner of the table, with the hardware modem board on the top. The board between the flight unit and the closest laptop computer is an old TNC-2 being used to talk to the CPU A engineering unit between the computers. The grey block on the table is a pair of old HP switching power supplies making 10V and 28V DC to simulate the spacecraft environment.
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  Bdale Garbee, KB0G, runs tests on the Rudak flight backup unit (shown in the middle of the picture opened up with CPU A vertical and CPU B horizontal) while Jim White, WD0E, and Harold Price, NK6K, work on porting SCOS in the background at another table.
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  A closeup shot of the flight backup hardware undergoing tests. The ROM emulator attached to CPU B is clearly visible. The big black and white rectangles on each CPU are the memory arrays. Each CPU has 16meg of fully error-corrected memory. The memory array is made up of custom SIMM sticks with 25ns static RAM chips, all of which are sandwiched with aluminum used to conduct heat away and help provide additional shielding. The white stuff is the space-rated goop that sticks it all together.
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  Harold Price, NK6K, in the foreground, and Jim White, WD0E, in the background, working on a problem with the DMA controllers on a CPU A engineering unit. The DMA controllers move data in and out of the serial interface chips that are attached to the modems, and are therefore fundamental to Rudak's operation. The CPU board is behind Harold's laptop. The two pieces of test equipment in the lower right are an HP 54645D Mixed-Signal Oscilloscope loaned by HP's Electronic Measurements Divisions for our use over the weekend, and an HP54620A Logic Analyzer which they graciously donated to the project. Both were in constant use through the weekend as the operating system port turned up issues in the hardware that needed to be understood and resolved. Harold spent much of the weekend trying to figure out how he could get the 54645D out of Bdale's basement without anyone noticing... The division of HP that made these products is now part of Agilent Technologies.
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  A closeup of the 54645D screen during a typical DMA transfer test. Shown are a few control signals, a few low-order address lines, and 8 bits of data bus.
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  The CPU A engineering unit under test in the previous two photos. The yellow wires toward the left rear represent wiring changes made during the DMA testing. The grey wires are probe leads from the HP instruments.
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  A screen-shot taken seconds after the Rudak A CPU engineering unit ran the SCOS kernel successfully for the first time. There was much rejoicing in the basement! This was a major milestone for the team.
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  Unfortunately, CPU A on the flight backup stack was badly damaged by a power wiring problem during initial turn on. In this photo, Chuck Green, N0ADI, and Bdale Garbee, KB0G, work to recover the RAM array from the smoked CPU board in hopes of reusing it. Chuck is cutting away PC board material from the bottom of the memory block using a rotary tool with a cut-off wheel, while Bdale holds the vacuum cleaner hose nearby to keep the dust under control. John Conner, WD0FHG, will perform exhaustive re-testing of this RAM array to determine whether it was damaged in the power event. If not, we'll install it on a new CPU A for the flight backup stack. If so, we'll retrieve any working pieces for engineering units and toss the rest.
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  The RAM block, upside down, after removal of the CPU PC board material. The three wires in the center are from the thermistor buried in the RAM array. This photo is mostly a demonstration of how well Lyle's digital camera can take close-up photos... we were all very impressed! You can even read the value of the SMT resistor behind the wire leads...

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  This is a shot of the the RUDAK CPUB V53 processor board in the background and the DSP modem prototype board in the foreground.

  The large silver-colored blocks on the far left of the DSP board are AD9042 12-bit, 41 MHz A/D conveters used in the "front end" of the IF receivers. The maze of logic analyzer clips to the rigth are sampling various timing signals during the debug of the V53 -> DSP loading circuitry.

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  This is a closeup of the right side of the previous shot. The ADSP-2171 in the foreground is a dedicated Modulator. It drives the AD7008JP50 direct digital synthesizer (DDS) chip at center-right in the image. This provides fine control of frequency and amplitude of complex signal waveforms for creating downlink signals.

  Immediately to the left of the DDS is a HArris HSP50016 digital downconverter (DDC) ship. This is a receiver-on-a-chip which accepts the A/D output of the AD9042 in the previous photograph. It has an internal complex local oscillator, mixer and matched 128-tap FIR filters for demodulaion of an IF waveform to baseband. This chip feeds the ADSP-2171 DSP chip in the background, which is dedicated to demodulation.

  There are eight such blocks in the final board, for a total of 16 DSPs!

  The circuitry to the right comprises interface buffers and decoders for the DSP modem board.

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  This shot of the HP54620A Logic Analyzer (provided courtesy of a division of Hewlett-Packard that is now part of Agilent Technologies) was taken during initial debug of the DSP modem board. The negative pulses on the line "!DSPCS" time the sequence and are derived from the V53 host processor on the RUDAK CPUB board. The first pulse resets the ADSP-2171 chip. The second loads a count telling the DSP chip how many bytes to expect. The load occurs in groups of three. The DSP uses a 24-bit program word, and the "host interface" is only capable of loading 8 bits at a time. It takes about 6 uSec/word to accomplish a load.

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  Shot of hardware modem PCB. 4 9K6 FSK, 2 153K6 PSK, power supplies, ADC. Large pair of shiny cases are TXCOs to make doppler orbit measurements from the recovered bit stream (rather than RF carrier).
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  Shows IFR FM/AM1200S measurement of FSK deviaiton - 3 kHz.
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  Recovered audio from IFR demodulator. SLightly nonlinear modulation, but clean.
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  CPU B engineering unit used to drive modems for testing.
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  Partial view of lab at WA7GXD showing part of test gear being used to test and align the modems. Note that these modems operate at P3D IF, not baseband.
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  Spectrum analyzer display of a typical 9K6 FSK RUDAK IF modem. Filters aren't the greatest in this piece of test gear, so spectrum appears wider than it really is.
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  Output of 153K6 PSK modem with convolutional encoder ON and "stuck bit" at TX data intput. The resulting modulation is a sine wave at 76.8 kHz. Here we see a classic "two tone" test pattern (PSK is really DSB suppressed carrier). The peaks are 153.6 kHz apart. The second set of peaks - the 3rd order "IMD" - is more than 30 dB below the peaks, or more than 36 dB below PEP. Plenty clean enough for P3D!
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  The is the same scale as before, but instead of the convolver, the "stuck bit" is applied to a scrambler and the convolver is OFF. This gives us a pseudo-random bit stream and we can see the occupied spectrum. Horizontal divisions are 100 kHz, vertical divisions 10 dB. Note that the occupied spectrum is quite narrow and easily fits into the P3D digital passband. By the time the energy reaches the analog passband it is 60 dB or more down from PEP.
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  This is the other PSK modulator - unshaped. Note how wide and slowly decaying the spectrum is.
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  Even in the wide mode, this notch is the second null in the previous spectrum display with slower sweep and narrower filters. The center frequency, 10.95 MHz, is the "enigneering beacon" downlink. Here the energy from the PSK modulator is more than 80 dB below peak, so the 400 bps PSK beacon would suffer virtually no disturbance from the PSK modulator.

  Spectrum shaping can be applied like this, with good planning, to allow spread spectrum (wideband) and narrowband communications to peacefully co-exist :-)

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  The HP 54645D Mixed-Signal Oscilloscope prototype Bdale borrowed for the weekend's festivities. It combines a two-channel oscilloscope and a 16-channel digital timing analyzer that are time correlated. We were all mumbling about putting one on our wish-lists by the end of the weekend. Our thanks to the HP Electronic Measurement Division for loaning us a prototype!
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  Lyle Johnson, WA7GXD, pauses for a moment to ponder the big hairy guy with the camcorder...
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  Lyle and John Conner, WD0FHG, figuring out what to test next.
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  A boring picture of the DOS (left) and Linux (right) machines that Bdale Garbee, KB0G, absorbed screen-glow from for most of the weekend... it's hard to turn on hardware without a little software, more or less!
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  A shot of the Rudak V53 CPU board, with EPROM emulators in mid-picture, Lyle's finger pointing to the A/D converter chip we were testing at the time, the ground-support interface cable to the adjacent PC in the lower left, and scope probes, logic analyzer cabling, and jumpers everywhere.
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  A closeup of the V53 CPU board. To the right is one of the EPROM emulators sitting atop an adapter board that makes it look like the 2kx8 fused-link PROMs that we will fly on the sattelite. In the rear is the CPU chip, the A/D converter is in the lower center of the shot, and some "grass", or jumper wires, are visible in the middle of the board. Also of great significance in this shot is one of the two QuickLogic FPGA's that condense a large amount of logic into a small space. One is used for the EDAC control, one is used primarily for chip select logic for all of the I/O devices on the board.
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  A birds-eye view of the V53 board, this time showing two of the SRAM SIMMs that were designed for Rudak and the original P3D GPS receiver CPU boards. Also shown in the center of the picture are the large number of large IC's for the serial ports and associated DMA controllers. In the bottom of the shot, a rat's nest of logic analyzer cabling gave us the ability to output data to the interprocessor communications port (which in flight will be used to allow the two V53 boards to communicate), so that we could easily observe program execution related to other timing events on the board.
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  Another overall view of the debug environment, as Lyle probes a chip select on one of the NEC 72001 serial port chips.

Photo rudak.gif, counterclockwise from lower left:

• Peter Guelzow, DB2OS
• Lyle Johnson, WA7GXD
• Harold Price NK6K
• Chuck Green N0ADI
• and Bdale's arm reaching for more of the tasty "Vinegar and Salt" potato chips!

• Peter Guelzow, DB2OS,
• Chuck Green, N0ADI
• Harold Price, NK6K
• Lyle Johnson, WA7GXD
• Jeff Ward, G0SUL/K8KA,
• Bdale Garbee, KB0G

• Chuck Green, N0ADI
• Jeff Ward, G0SUL/K8KA,
• Harold Price, NK6K
• Lyle Johnson, WA7GXD
• Peter Guelzow, DB2OS,
• Bdale Garbee, KB0G