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Incremental phase modulator

Hi Guys,

I found the enclosed snippet on the web and it looks useful. Do any of
you know how I could go about implementing it? I have a CPLD "starter
kit" that I am learning to drive (slowly!!).

> Incremental Phase Modulator (IPM) -- simply use a clock that is 4 to 16 times the chip rate clock for the system digital timing reference in the receiver.  Follow this clock with a programmable frequency divider, e.g. if the clock is 4 x the PN chip rate, use a divide by 3/4/5 counter. In the case of a clock at 8 x the PN chip rate, use a programmable 7/8/9 counter.  Make sure this counter is controlled in such a way that it adds or drops only one input clock each time it is adjusted. This gives us single PN chip phase adjustment capability! Also, make sure that the counter can be advanced or retarded only once per data bit time (or one PN Epoch)!  This scheme is especially useful in designs using FPGAs or planning to use custom ASICs, because it lends itself to simple, straightforward digital implementation.  Note that, by proper design, ONLY advancing OR retarding of the PN chip phase is necessary -- but be careful of long term PN clock oscillator drifts!

    73 de Geoff vk2tfg

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