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Launch Pad Return

IHU3 Files


The IHU3 project is being done in the open. This is a controller that runs the IPS language orignated by Karl Meinzer, DJ4ZC. The IHU3 uses CAN bus modules for most I/O.

This page has been redesigned based newly available information (Oct 2008). The original AMSAT IHU3 page has some different documentation files and is available here for archival purposes.


The following schematics are available in Portable Document Format (PDF). No further information is available on these at this time.

IHU3 Schematic.

Note: In the oscillator on sheet 3, C58 should be changed to 33 pF, C60 to 100 pF.

Various logic files used in the FPGAs. Clock and Watchdog and EDAC and Decode are top level diagrams. The various blocks they use are listed below.

4029BINUP binary counter.

CLKSYNCCHK clock synchrnization checker.

CTR2_12 12-bit counter.

CTR2_19 19-bit counter.

DECODE38 3 in, 8 out decoder.

DIV3125 divide-by-3125.

EDAC memory error detection and correction block.

EDAC8M 8-bit error detection and correction slice.

FLASHADR Flash memory address comparator.

MUX8 8 channel multiplexer.

PN127F 127-bit sequence comparator.

PN127W 127-bit sequence comparator. This uses an incorrect sequence.

SR16WPRE 16-bit shift register.

TLMENC telemetry encoder.

WATCHDOG upper level CPU watchdog.

Other Files


Updated 2006 Dec 24

The programmable logic for the IHU3 is done with QuickLogic Antifuse parts. Originally, the pASIC2 series parts were used. They have since become obsolete and the design is being migrated to the pASIC3 components. The basic tools are available at no cost from the QuickLogic web site.

These are the design files for the EDAC and Decode FPGA. At this time, this logic has not been completely tested, but appears to work.

These are the design files for the Clock and Watchdog FPGA. At this time, the warm reset logic PRSG is incorrect, and the "reset strategy" logic has not been fully tested. There may be significant problems with this logic.

Here are the Clock and Watchdog programming files for the QL3012-1PF144I (or other speed grade/temp range). This is the current version with the incorrect PRSG sequence for the PN127W function.

Here are the EDAC and Decode programming files for the QL3012-1PF144I (or other speed grade/temp range).


Here is the binary image for the CPU boot Flash.


The PCB layout was done using OrCAD. The PC boards are still being debugged, so there may still be errors in the design.

The Gerber files are in a "zip" archive.

The OrCAD design files are also in a "zip" archive.

The PCB layout has one known problem: U26 pin 2 is floating. It needs to be connected to VAref, which is available on the side of C122 which conencts to U48 pin 3.

Open Issues

This issue may be resolved -- stay tuned!

The first instance of current design had a reset anomaly that resulted in a CPU hang. Click here to see a screen shot of some details of the relevant signals captured by a logic analyzer. Click here to see a screen shot of the overall timing relationship of the reset problem as captured by a logic analyzer. After analysis, a new FPGA was programmed and the problem disappeared. It appears the problem was with the particular FPGA rather than the design, but more instances will need to be built to confirm this.


Some parts have become difficult to obtain in the years since this project was initiated.

U15: 74FCT245

NXP 74ALVC16245DGG. This part will tolerate a 5V "B" supply.

U29: 74FCT16245

NXP 74ALVC16245DL; TI 74LVC16245ADL. The TI part will *not* tolerate a 5V supply, but in this position only 3.3V is required.

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